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IUMA Projects and activities Las Palmas de G.C., Dec. 1999 Examples of projects Creation of a ciphering engine using RISC and cryptographic circuits for ISDN applications Implemention of a VIS in SPARC V.8 for cheap multimedia applications High-level synthesis system for DSP circuits Implementation of electronic systems in MCM with Cadence/Allegro Algorithms for multimedia in the MVP (TMS320C80) development system. ... Las Palmas de G.C., Dec. 1999 JavaRISC Project Hardware implementation of the JAVA Virtual Machine usign RISC style architecture Synthetized from a RT Level VHDL description using Synopsys and Cadence Implemented in CMOS ES2 0.7 mm technology Las Palmas de G.C., Dec. 1999 T-DES Project Interchip Digital Link Interface for direct connection to ISDN Triple DES Cipher Algorithm Synthetized from VHDL using Synopsys and Cadence Results for ES2 CMOS 0.7 mm: 4.944 gates 59015 transistors 15.6 mm2 Peak throughput: 256 kbps Las Palmas de G.C., Dec. 1999 CEIP Project: Cipher Engine for ISDN Includes: 2 Flash-RAM Chips 4 Static RAM 1 microcontroller RISC 15 T-DES CFB Chips 1 ASIC Las Palmas de G.C., Dec. 1999 ATM project Micro machined alignment Multi Chip module H-GaAs-IV Laser diode Photo diode ATM Physical Layer Trans conductance amp Clock recovery Cell delineation Error recovery HEC generation 16 16 C-GaAs ATM Layer VPI label translation Policing Routing label 16 H-GaAs-IV Switch fabric 16 RX/TX SRAM CPU Operations and management Las Palmas de G.C., Dec. 1999 ATM Project (FIFO) Las Palmas de G.C., Dec. 1999 ATM Project (test bench) Las Palmas de G.C., Dec. 1999 ATM Project (test bench) Las Palmas de G.C., Dec. 1999 Fast Fourier Transform Project Processing unit process every butterfly Routing unit Fi [k ] Fi1[k ] M Fi 1[ k i ] 2 Processing unit Routing unit. Fi [k Mi ] 2 Las Palmas de G.C., Dec. 1999 Fast Fourier Transform Project Processing Unit a a b WMk b a - b WMk + a a´ i i b WNm + - - b´ 2k 2k bI sen a R a R bR cos i i 2k 2k - bR sen a I a I bI cos i i 2k 2k bI sen bR a R - bR cos i i 2k 2k bI a I - bI cos - bR sen i i Las Palmas de G.C., Dec. 1999 Fast Fourier Transform Project 1. Initial stage 1 2. Scale factor 3. radix2/radix4 combination N -1 2 K n (1 d 4 - 2i 3 ) i 0 4 2 4. di coefficients stored in a ROM 7 5. Post-processing 5 6. Vector Merging Adder 6 7. Control Unit Las Palmas de G.C., Dec. 1999 Fast Fourier Transform Project Convergence and scale factor for N=16 and = /3 radix2 1,4 radix4 repeat scal. 1,2 1 Escale 0,8 factor 0,6 0,4 0,2 zi 0 Convergence -0,2 0 2 4 6 8 10 12 14 16 18 Iteration Las Palmas de G.C., Dec. 1999 Fast Fourier Transfor Project (results) Delay Unit Delays and power dissipation FFT Processor characteristics Radix2 Radix4 D-FF Buffers VMA Process spread FF1h 100º TT 75º SS2 0º FF1h 100º 441 626 173 48.2 744 Tcycle (ns) 1.15 1.20 1.40 TT 75º 499 650 191 60.0 810 Power SS2 0º FF1h 100º 721 741 225 102.4 1070 10.7 17.8 1.93 3.30 695 TT 75º SS2 0º 9.0 15.3 1.92 2.66 588 7.3 10.2 1.3 1.8 390 Frecuency (MHz) 870 825 700 Power = 12,5 W Area = 5732 x 6070 mm2 (35 mm2) Encapsulated = LD256 Las Palmas de G.C., Dec. 1999 t ciclo t D - FF tbuffer t radix4 t setup t skew Fast Fourier Transfor Project (results) Comparison with other architectures Type Programmables Multiprocessors Chip sets for FFT ASICs Company and model Analog Devices ADSP-21060 Intel 860 XP Texas Instruments. TMS320C80 Sharp Electronics LH9124/LH9320 Plessey PDSP16510 Butterfly DSP BDSP9124 Dassault Electronic UFFT (6 IC) IUMA CFFT CORDIC based 1024 points CFFT (ms) 460 550 163 87 96 54 12,8 8 Las Palmas de G.C., Dec. 1999 VSC851 Project The Crosspoint Switch has 32 data inputs and 32 data outputs. Any input can be multiplexed to any, some or all outputs. Signals in data path are fully differential to minimize duty cycle distortion and achieve an excepcional signal fidelity. The switch is configured by sequentially loading each multiplexer’s 5-bit Holding register with the desired input address D[4:0]. When complete, a high pulse is applied to GSTROBE and all new configurations are simultaneously transferred into the switch multiplexers. Switch Matrix I+[0:31] Z+[0:31] 32x32 Switch Matrix I-[0:31] Z-[0:31] Control Logic A[4:0] BROADCAST FLOWTHRU D[4:0] 5 to 32 decode 32 32 5 32 32x5 Holding Registers 32x5 Control Latches 0,1, ... ,31 LSTROBE GSTROBE Las Palmas de G.C., Dec. 1999 VSC851 Project Control Logic Switch Matrix Las Palmas de G.C., Dec. 1999 VSC851 Project Las Palmas de G.C., Dec. 1999 VSC851 Project (testing procedure) In order to test the 1.6 Gb/s 32x32 Crosspoint Switch, a characterization board was designed. This board allows to measure the following parameters: • Propagation Delay. • Duty Cycle Distortion. • Output Skew. • Minimum Input Pulse Width. • Maximum Bit Rate. • Jitter & Interchannel Coupling. (Channel 0) 2 sets side launch SMA 1 st Crosspoint Switch 31 All 50 terminated differential connections 2 nd Crosspoint Switch ( DUT) In BROADCAST mode Test Out Control DIP switches Las Palmas de G.C., Dec. 1999 32 VSC851 Project (testing procedure) Las Palmas de G.C., Dec. 1999 VSC851 Project (testing results) Four boards with chips from different lots were tested. According with the test, the Crosspoint Switch is fully functional @1.6Gb/s with a 90% of nominal differentialDescription amplitude. Min Max Conditions Minimum input pulse width 600 ps — Propagation delay — 1.88 ns Duty cycle distortion — 150 ps Output to output skew — 250 ps Maximum bit rate — 1.8Gb/s Interchannel coupling — 94 mV Worst case 60/40 input duty cycle — At 1.6 Gb/s On a given part broadcast mode Differential ECL output voltage higher than 600mV At 1.6 Gb/s Las Palmas de G.C., Dec. 1999 VSC851 Project (comparative results) Product MaximumData Rate Propagation Delay Output to Output skew Power Supplies Power Dissipation TQ8032 800 Mb/s 2.3 ns 500ps -5V& +5V 13.8 W IUMA32x32 1.8 Gb/s 1.88ns 250ps -2V& +3.3V 9W Las Palmas de G.C., Dec. 1999 VSC851 Project Power consumption: 9 W Duty cycle distortion < 150 ps 1st case: 5 ms to “0” and 1010 ... = 265 ps on “1”, 142 on “0” 2nd case: 010101 ... and 00000101 Propagation delay = 1,8 ns Output to output skew < 300 ps Minimum pulse width = 720 ps Packaging = 256-pin LDCC Power supply: -2V y 3,3 V Output level: 3,3 V TTL y ECL differential Las Palmas de G.C., Dec. 1999 OLYMPO Project Las Palmas de G.C., Dec. 1999 Summary Research and development projects funded by European Union, Spanish government , Canary government and industries. CMOS, GaAs and SiGe technology based. Projects for digital processing, communications, computers, CAD tools... Around 20 researchers involved in these projects. Las Palmas de G.C., Dec. 1999
