Download Group and individual assignments

EX1B Part 2
3GM11
Every cooperative group have to build three different VHDL-only projects for the sPLD 22V10 or the ispMACH4128V CPLD chip.
Projects’ locations and file names:
(dropbox or Sky Drive or Google Drive)
[dropbox]/EX1B/Part2/Chip_74138/
/ Chip_74138_gates/ Chip_74138.vhd
/ Chip_74138_behavioural/ Chip_74138.vhd
/ Chip_74138_blocks/ Chip_74138.vhd
Each project has to be tested using the same VHDL test bench file named Chip_74138.vht
Cooperative groups
M_G11
CARRILLO NAVARRO, VICTOR
M_G11
M_G11
MARTIN PEREZ, IVAN
SERRANO JIMENEZ, ESTER
EX2B, Part 2 entity assignment Chip_74138
Three architectures :
Gates (Minimised (using SoP or PoS) or canonical equations
(using maxterms or minterms))
Behavioural (Truth table or description algorithm)
Blocks (Hierarchical design cascading smaller components of
the same kind: DEC 2:4 for the 74LS138)
M_G12
MASIP COSIN, SERGI
M_G12
PÉREZ GARCÍA, RUBÉN
PICAZO DELGADO, SERGI (3GT3 ??) [*]
Blocks
Gates
Behavioural
M_G13
M_G13
M_G13
GOGONEA, ROXANA MADALINA
MENDO SIERRA, NATALIA
MURILLO LÓPEZ, ERIC
Behavioural
Blocks
Gates
M_G14
M_G14
M_G14
ASENSIO MALO, RICARDO
MONTILLA ROS, LAURA
URTASUN LOPEZ, XAVIER
Gates
Behavioural
Blocks
M_G15
M_G15
M_G15
FLORIT MIR, JOAN IGNASI
IGLESIAS GIMENO, JORDI
RAMOS SANCHEZ, ALEJANDRO
Blocks
Gates
Behavioural
M_G17
M_G17
M_G17
GARCIA CASALS, ARNAU
GOMEZ BLAZQUEZ, ALBERTO
SUAREZ BALAGUER, CARLOS
Behavioural
Blocks
Gates
M_G18
M_G18
M_G18
ENRECH CINTERO, OCTAVI
SOTO TORRES, SERGIO
ATUCHA ZAMBRANO, PEDRO ANTONIO
Gates
Behavioural
Blocks
[*] As soon as possible, you have to make official the change of group, or you have to go back to class 3GM31 where you are
actually matriculated.
Students from class 3GM11 who has the same design can make an informal “experts” group to learn about the assigned
technique (puzzle or jigsaw), so that it is going to be easy to design the problem, and they can come back to their cooperative
group to explain it better to their team mates. The aim is that each cooperative group master the three architectures for the
assigned chip.
EX1B Part 2
3GM12
Every cooperative group have to build three different VHDL-only projects for the sPLD 22V10 or the ispMACH4128V CPLD chip.
Projects’ locations and file names:
(dropbox or Sky Drive or Google Drive)
[dropbox]/EX1B/Part2/Chip_74148/
/ Chip_74148_gates/ Chip_74148.vhd
/ Chip_74148_behavioural/ Chip_74148.vhd
/ Chip_74148_blocks/ Chip_74148.vhd
Each project has to be tested using the same VHDL test bench file named Chip_74148.vht
Cooperative groups
EX2B, Part 2 entity assignment Chip_74148
Three architectures :
Gates (Minimised (using SoP or PoS) or canonical equations
(using maxterms or minterms))
Behavioural (Truth table or description algorithm)
Blocks (Hierarchical design cascading smaller components of
the same kind: ENC4:2 for the 74LS148)
M_G01
FERRERI JIMENEZ, DAVID
M_G01
M_G01
MOZOS RUIZ, JOSE MIGUEL
RODRIGUEZ LEGUA, GUILLEM
M_G02
M_G02
M_G02
LEIVA CABELLO, MANUEL
RODRÍGUEZ PIÑERO, RUBÉN
SANCHEZ CABANA, ALEJANDRO
Blocks
Gates
Behavioural
M_G03
M_G03
M_G03
CARO TORRES, CARLOS JAVIER
CORTES BRAVO, REBECA
TIERNO RUIZ, ALEX
Behavioural
Blocks
Gates
M_G04
M_G04
M_G04
BAENA NAVARRO, MANUEL ALEJANDRO
FRAGO ALVAREZ, IVAN
VALLS MARIN, ALBERT
Gates
Behavioural
Blocks
M_G05
M_G05
M_G05
JEREZ PATIÑO, SERGIO
RUIZ BALDOMA, ALEX
VIVAS GIL, DANIEL
Blocks
Gates
Behavioural
M_G06
M_G06
CALVERA SANCHEZ, DANIEL
SERRA ROIG, JORDI
Behavioural
Blocks
CUADRADO BLANCO, NÉSTOR
[**]
[**] Does anyone know this guy? Can you tell him to contact me as soon as possible?
Students from class 3GM12 who has the same design can make an informal “experts” group to learn about the assigned
technique (puzzle or jigsaw), so that it is going to be easy to design the problem, and they can come back to their cooperative
group to explain it better to their team mates. The aim is that each cooperative group master the three architectures for the
assigned chip.